1. Field of the Invention
The present invention relates to reprogrammable nonvolatile semiconductor memory devices such as EPROM and EEPROM, and more particularly, to a method for writing data to a multilevel cell able to store more than one bit of information in a single memory cell.
2. Related Background Art
A multilevel data storage nonvolatile semiconductor memory device which can store three or more levels of data (for example, four-level data: “00”, “01”, “10”, and “11”) in a single memory cell (EEPROM with NOR cell architecture) as a means to increase data density of reprogrammable nonvolatile semiconductor memory such as EPROM and EEPROM are disclosed in Japanese Unexamined Patent Application Publication No. H04-57294 and H10-302482, for example.
Data writing to the multilevel nonvolatile semiconductor memory employing a data readout system that performs batch verification of N (N≧3) level data is generally performed as follows. Initially, a write operation that injects electrons into a floating gate is performed on a memory cell for a given period of time (about several hundreds of seconds). Next, a read operation for verification, which is referred to hereinafter as a verify-read operation, is performed.
Then, a compare operation is performed to compare a data level read out by the verify-read operation with a data level (expected level) to be written, thereby determining whether the threshold level of the memory cell that has been written exceeds the write level corresponding to the expected level. For the memory cell where the threshold level does not exceed the write level corresponding to the expected level and thus a verification result is “FAIL”, the write operation is performed again for a given period of time.
In this manner, a cycle of the write operation, verify-read operation, and compare operation is repeated until the written threshold level of the memory cell exceeds the write level corresponding to the expected level. Once the threshold level exceeds the write level, that is, the verification results in “PASS”, the write operation is no longer performed on this memory cell. The writing in the nonvolatile semiconductor memory device is completed when the write level corresponding to the expected level is reached in all the memory cells.
Referring first to FIG. 6, it schematically shows the ID-VG characteristics of a programmable nonvolatile semiconductor memory cell changing during the writing of one of four-level (two-bit) data to the cell. The diagram shows the ID-VG characteristics when data is erased with a solid line. After the write operation to the memory cell is started, the ID-VG characteristics changes so that the threshold level increases each time the writing (electron injection into the floating gate) is performed as shown with dotted lines. Thus, the enhancement state of the memory cell changes accordingly.
After the each writing to the nonvolatile semiconductor memory cell, the gate voltage is changed into a word voltage VW 1 for the read operation to read the write level LV of each memory cell. The write operation to the cell stops at the point when the read level reaches the write level corresponding to the expected level of this memory cell, which is, the point when the read current level exceeds the write level corresponding to the expected level indicated by a circle in FIG. 6. Desired data writing is thereby achieved.
In the case where the expected levels for the four levels (“11”, “10”, “01”, and “00”) stored in a plurality of nonvolatile semiconductor memory cells connected to a single word line are LV1, LV2, LV3, and LV4, if the write operation is performed per word line, the writing to the cell for storing the data “11” is completed first and no writing is performed on this cell after that. When the writing to the cell for storing the data “00” is finished, the writing operation to the cells connected to this word line is completed. Since a data erase operation usually resets the cells to the state having the data “11”, the data write operation skips the writing to the cell for storing the data “11”.
FIG. 7 is a block diagram schematically showing a conventional data write circuit configuration for multilevel nonvolatile semiconductor memory. In the configuration shown in FIG. 7, the nonvolatile semiconductor memory has cell array architecture. The address of each cell is selected by a X-decoder 21 and a Y-decoder 19. A data writing control circuit 100 is encircled with a dotted line in FIG. 7. The data writing control circuits 100 are provided to be of the same number as the memory cells in which writing or reading is performed at the same time. The memory cells 15 where writing or reading is simultaneously performed are selected by the X-decoder 21 and the Y-decoder 19. Data writing or data reading is performed on each of the selected memory cells 15 by the operation of each data writing control circuit 100 connected to each cell through the Y-decoder 19.
Each data writing control circuit 100 includes an I/O buffer 11 for inputting the write data specified by a user to the nonvolatile semiconductor memory cell 15 connected to the data writing control circuit 100 via the X-decoder 21 and the Y-decoder 19 and outputting to the outside the stored data read out of the nonvolatile semiconductor memory cell 15 by the read operation. It also includes a data register 12 for holding the write data from the I/O buffer 11 and outputting the write data as expected level data, and a write circuit 13 for conducting writing into the nonvolatile semiconductor memory cell 15 according to the expected level data. Also included is a sense amplifier 14 for reading out a write level state of the nonvolatile semiconductor memory cell 15, a MLC decoder 16 for decoding the write level of the memory cell read out by the sense amplifier 14, and a compare circuit 17 for comparing the data decoded by the MLC decoder 16 with the expected level data retained in the data register 12 and outputting a verification result.
An address buffer 50 outputs address information of the memory cell where data writing or reading is to be performed to the X-decoder 21 and the Y-decoder 19. A power unit 20 supplies a predetermined word voltage and source voltage according to each operation to a word line and a source line, respectively, to which the nonvolatile semiconductor memory cell 15 is connected so as to perform data write, read, or erase operation on the nonvolatile semiconductor memory cell 15.
A reference current generator 40 switches between a reference current for verification in data writing and a reference current in data reading from the memory where multilevel data is written according to each read operation, and outputs either current to the sense amplifier 14.
If the sense amplifier 14 corresponds to each bit line, the writing can be performed per word line. In this case, the same number of the data writing control circuits 100 as the number of the memory cells connected to one word line are provided, which undesirably makes the chip size larger. Thus, the number of the sense amplifiers 14 is usually set equal to the number of the memory cells from which data is read out in parallel in the data read operation on the nonvolatile semiconductor memory. Further, the number of the memory cells to which data is written at the same time, which is, the number of the data writing control circuits 100, is also set equal to the number of the sense amplifiers 14. The memory cells 15 on which writing are performed is selected by the X-decoder 21 and the Y-decoder 19.
FIG. 8 is a block diagram showing a conventional write circuit configuration where the write circuit configuration shown in FIG. 7 is applied to the nonvolatile semiconductor memory having the memory cell 15 able to store four-level (two-bit) data.
In the configuration shown in FIG. 8, when performing verification in data writing, the sense amplifier 142 to 144 output a signal that changes from “H” to “L” (or “L” to “H”) when a write level state of the nonvolatile semiconductor memory cell 15 exceeds the expected level LV2, LV3, and LV4, respectively, that is, when the current falls equal to or below the reference current level IR2, IR3, and IR4, respectively. Further, though not shown, there is provided a data erase circuit having a sense amplifier for detecting the expected level LV1 to control a data erase operation so that it resets the cells to the state that all the cells have the expected level LV1 (data “11”) when data is erased.
The compare circuit 17 outputs “FAIL” if the write level of the expected level data retained in the data register 12 is higher than the write level of the read data output from the MLC decoder 16, or “PASS” if the write level of the expected level data is equal to or lower than the write level of the read data.
FIG. 9 shows the distribution of the ID-VG characteristics of the nonvolatile semiconductor memory cell where one of four levels is written by the data writing control circuit 100 shown in FIG. 8. A conventional data write operation will be explained hereinafter with reference to FIGS. 8 and 9.
Prior to the write operation, an erase operation is performed by an erase circuit (not shown) to erase previous data stored in the nonvolatile semiconductor memory cell 15. All the memory cells in the nonvolatile semiconductor memory device thereby have the expected level LV1 (stored data “11”). The write operation is then started, inputting write data for each memory cell from each I/O buffer 11 to the data register 12. The data register 12 retains the write data as expected level data and outputs it to the write circuit 13.
If the expected level data from the data register 12 is “11”, the write circuit 13 does not perform the write operation on the corresponding memory cell 15 since writing is already completed there. On the other hand, if the expected data from the data register 12 is “10”, “01”, or “00”, the write circuit 13 performs the write operation on the corresponding memory cell 15 for a given period of time (about several hundreds of seconds), injecting electrons into the floating gate of this nonvolatile semiconductor memory cell 15.
Next, the read operation for verification (verify-read operation) is performed on the memory cell 15. If the current read out of the memory cell 15 is greater than the reference current IR2, all of the sense amplifiers 142 to 144 output “H”, and the MLC decoder 16 outputs the read data “11”. As a result, while the compare circuit 17 for the memory cell 15 with the expected level data “11” outputs the verification result “PASS”, the compare circuit 17 for the memory cell 15 whose expected level data output from the data register 12 is “10”, “01”, or “00” outputs “FAIL”. Thus, the write cycle on this memory cell 15 is performed again.
The threshold level of the memory cell 15 increases with each write cycle. At the point when the current read out of the memory cell 15 falls equal to or below the reference current IR2, the output from the sense amplifier 142 becomes “L”. Thus, the outputs from the sense amplifiers 142, 143, and 144 are now “L”, “H”, and “H”, respectivelly, and hence the MLC decoder 16 outputs the read data “10”. The verification result in the compare circuit 17 connected with the memory cell 15 whose expected level data retained in the data register 12 is “11” or “10” thereby becomes “PASS”.
The “FAIL” or “PASS” result is sent also to the data register 12. Upon receiving the “PASS” result from the compare circuit 17, the data register 12 changes the stored expected level data into “11”. Thus, the expected level data “11” is input to the write circuit 13 for the memory cell 15 whose expected level data has been “10”. The memory cell 15 is now in a writing completion status, and no write operation is performed there after that.
On the other hand, in the write circuit for the memory cell whose expected level data output from the data register 12 is “01” or “00”, the verification result is still “FAIL”, and hence the write cycle on the relevant memory cell 15 is performed again. The write cycle is repeated in this manner, and data writing is completed then on the memory cell with the expected level data “01”, and finally on the memory cell with the expected level data “00”.
FIG. 9 shows the ID-VG characteristics of the nonvolatile semiconductor memory cell into which one of four levels is written by the data writing control circuit 100. As shown therein, variation in the ID-VG characteristics of each cell becomes larger with the distance away from a verification determination point indicated by a circle in FIG. 9. In order to prevent a read margin from decreasing in the data read operation due to this variation, a word voltage VW in the verification operation and a word voltage VW in reading out data from the memory are set at the same level VW 1. A data readout determination point indicated by a triangle in FIG. 9 from the memory storing multilevel data is set at a midpoint between the verification points indicated by circles in FIG. 9.
Further, the expected levels LV1, LV2, LV3, and LV4 and the readout word voltage VW 1 are determined considering the condition for keeping all the memory cells 15 to which data is written in the enhancement state, and the disturb characteristics of the memory cells.
If the memory cell 15 is in a depression state during the data writing, the current can flow also from a non-accessed memory cell on the same bit line, interfering with accurate reading of the current level (data level) from the accessed memory cell. Thus, a write level to the memory cell 15 is set at the level that the writing to the memory cell 15 is always in the enhancement state to allow an output current from a non-accessed memory cell on the same bit line to be always zero.
A positive word voltage VW is applied to a control gate when reading data from the memory. Due to this readout word voltage VW, the electrons injected into the floating gate in the data write operation can be slightly drawn to the control gate. This causes the stored data to be lost as the number of data reading increases, called cell disturb characteristics. Thus, the word voltage VW 1 in the data writing is preferably not very large.
As is obvious from the distribution of the ID-VG characteristics of the nonvolatile semiconductor memory cell shown in FIG. 9, the higher is the expected level LV1, the larger is the variation of the threshold level of the memory cell 15 where the LV1 is written, causing the memory cell 15 subject to be in the depression state. Further, if the readout word voltage VW 1 is too large, the disturb in the read operation can have serious adverse affects.
For the above reasons, the readout word voltage VW 1 and the reference current IR1 of the expected level LV1 are determined in consideration of the disturb characteristics of the memory cell 15 and the condition for keeping the memory cell in the enhancement state. All the memory cells 15 are reset to have the expected level LV1 by the memory cell data erase operation. The lower level is appropriately divided so as to save a read margin in the most effective manner.
Generally, the readout word voltage VW 1 is determined by a voltage range used for the word voltage VW of the memory cell 15 on the basis of disturb consideration, the maximum current of the memory cell 15, and the condition for preventing the memory cell 15 from being in the depression state. The current corresponding to the above voltage is then (N−1) divided, thereby ensuring the read margin.
The read margin in the nonvolatile semiconductor memory cell where one of four levels is written increases with the difference between the reference current IR1 for the expected level LV1 in the memory cell with the lowest threshold level (the cell in a data erased state), and the reference current IR4 for the expected level LV4 in the memory cell with the highest threshold level. It is thus preferred that the reference current IR1 of the expected level LV1 is the highest possible while the reference current IR4 of the expected level LV4 is the lowest possible.
Increasing the reference current IR1 for the expected level LV1 requires increasing the readout word voltage VW 1. The readout word voltage VW 1, however, is determined by the restriction of the disturb characteristics of the memory cell and the condition for keeping the memory cell in the enhancement state and preventing it from being in the depression state as described above. It is thus unable to increase the readout word voltage VW 1 as desired.
Given the above restriction, conventional techniques set the smallest possible reference current IR4 for the expected level LV4 to create a large difference between the reference current IR1 for the expected level LV1 and the reference current IR4 for the expected level LV4. Each write level (the expected levels LV1, LV2, LV3, and LV4) is then determined so as to create a read margin most effectively.
On the other hand, reducing the reference current IR4 for the expected level LV4 causes reduction in the sensitivity of the sense amplifier 144 to which the reference current IR4 is input. Thus, if the reference current IR4 for the expected level LV4 is too small, it may cause indeterminate sensing in the verify operation. There is thus a problem that the reference current IR4 for the expected level LV4 is restricted by the sensitivity of the sense amplifier 144.